The present invention relates to a method of manufacturing a substrate.
Hybrid integration of III-V compound semiconductors and (silicon) CMOS devices on a universal silicon-based platform is a promising approach to introduce new circuit capabilities and associated applications. Conventionally, silicon (Si) and III-V circuits are fabricated and packaged separately, before being assembled on a carrier substrate. But this approach is confronted by interconnect size and losses, which affect performance, form factor, power consumption, cost, and complexity of the assembled circuits.
More specifically, for hybrid integration of III-V and Si circuits, growing III-V materials directly on CMOS devices or Si-based substrates tend to be the simplest approach. However, growth temperature for III-V materials is usually too high to the extent of causing severe damage to the CMOS devices. For example, the growth temperatures for GaAs/InP and GaN are respectively about 650° C. and 1050° C. Also as an example, referring to a hybrid device 100 of FIG. 1, the hybrid integration requires integration of Si (100) on a Si (111) handle substrate through bonding, and specifically, the Si (100) orientation was chosen for the CMOS fabrication and the Si (111) orientation for GaN growth. Further, GaN is grown in recesses arranged on a face of the handle substrate, and so growth uniformity is more difficult to achieve, such that consequently an additional step is required to remove any overgrown GaN on the CMOS transistor area. But more importantly, a thermal budget for growing the GaN should not degrade any CMOS devices already present on the handle substrate and so, Plasma-Assisted Molecular Beam Epitaxy (P-MBE) is used to grow the GaN (i.e. P-MBE requires an operating temperature of 750° C., whereas Metalorganic Vapour Phase Epitaxy (MOCVD) however requires 1050° C.). It is appreciated that the thermal budget needed depends on materials used to manufacture electrodes of the CMOS devices. In modern foundries, the electrodes tend to be formed from cobalt silicide (at least for 0.18 μm technology), which degrades when subjected to a temperature greater than 550° C. and hence damaging the associated CMOS devices.
Alternatively, 3D wafer stacking, which combines bonding and layer transfer, is another way to integrate III-V compound semiconductors on a common Si platform. The reason why 3D integration is appealing is explained below. The device scaling method used in Si-CMOS, which provides a primary driving force for the semiconductor industry to reduce costs per transistor/maintain device performance/lower power consumption, is now reaching fundamental bottlenecks. Further shrinkage of CMOS devices not only makes the CMOS devices unreliable (i.e. due to short channel effects and random fluctuations) but also more expensive (i.e. due to lithography and more processes involved). In addition, the device scaling method is also approaching limits on both the physical-dimension and economical aspects. So to address the problem, 3D wafer stacking, which allows multi-core integration or co-integration with other materials, was proposed.
III-V materials (e.g. GaAs, InGaAs, InP or GaN) tend to have higher electron mobility properties than silicon-based materials. So integration of high speed III-V electronic devices has been proposed to improve performance of mixed-signal chips by integrating high speed/high power III-V FETs/HBTs with CMOS digital circuitries.
Another application is to utilise the optical properties of III-V compound semiconductors. III-V materials may be used as a light source and integrated with optical amplifiers and detectors onto Si chips, or waveguides to further enhance the performance and design flexibility for photonic interconnects. The III-V/Si hybrid devices may also be used as a light source to compensate the inability of silicon to act as a light source, due to silicon's low radiative recombination rate stemming from indirect energy bandgaps.
Fusion bonding of wafers is another useful approach to integrate III-V semiconductors and CMOS devices on a universal platform, in which fusion bonding may be carried out in atmospheric ambient and room temperature. A method to fusion bond Si (100) on GaN/Si wafer has been reported in literature, in which a single bonding process was used, but the method however suffers from some drawbacks: (i). the III-V materials and CMOS devices cannot be processed separately leading to cross-contamination issues, especially in foundries, and (ii). the III-V materials may have problems surviving the employment of high temperature CMOS processing steps. While nitride-based III-V materials may be able to survive the high temperature processing, it is however an issue for arsenide/phosphide-based III-V materials, since the latter start decomposing at about 350° C.
One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art.